Circuit designers often use software tools to aid their design process. The designer specifies the circuit to be designed using a high definition language (HDL) language (such as HDL or Verilog). The HLD is translated into a circuit design via synthesis software, such as Design Compiler, available from Synopsys, Inc. of Mountain View, Calif. The logic gates of the circuit design are then assigned a physical placement on an integrated circuit ("chip") using datapath placement software.
Conventional datapath placement software requires that the logic gates in the datapath be "regular," i.e., that each function in the datapath should operate on a collection of data inputs that contain multiple bits that are nearly identical. Thus, conventional datapath placement tools are constrained to use logic gates that are substantially the same for each bit. This regularity makes it easy to assign each logic gate to a position in the layout.
Unfortunately, state-of-the art synthesis software do not usually produce "regular" circuits. Conventional synthesis tools usually ignore the bit-by-bit regularity of datapath elements in order to obtain gains in optimization. A particular bit may be optimized very differently than its neighbors. Moreover, the function of neighboring bits may be merged together, making it difficult to assert with which bit a particular gate is associated.
Because logic gates produced by circuit synthesis tools are not regular, conventional datapath placement tools cannot be used on the output of circuit synthesis tools. Use of other conventional (non-datapath) placement tools carries inherent disadvantages. First, wiring that results from these other conventional placement tools may be longer than necessary on the average. Second, wiring that results from use of other conventional placement tools is much less predictable and controllable. Third, gate connections that result from use of other conventional placement tools are not easily combined with gate connections from standard datapath placement techniques.
What is needed is a tool to create a placement for non-regular configurations of logic gates (such as those created by circuit synthesis tools) that still maintains good wiring and integration with datapath placement.
Moreover, current placement current placement techniques are driven by one or more constraints. These constraints include 1) attempting to shorten wire lengths that connect logic gates together, 2) attempting to decrease congestion of connecting wires so that wires are not forced to run on top of one another, and 3) attempting to leave space between logic gates, where appropriate, to allow space for wires to run.
Some conventional placement tools have manual constraints whereby a user may tell the tool to place particular logic gates in a particular region of a chip. Other conventional placement tools force a logic gate to occupy an absolute position on a chip. Both types of constraints ("forced constraints") are absolutely binding as to the final position of logic gates. Forced constraints have the potential to cause the placement to be unfeasible or of inferior quality.